Physical Design Engineer

Job Description: Internal CAD Library development group is looking for an energetic, outgoing and self-driven professional to join our team. The candidate will develop CAD models and software to automate Cad model generation by working closely with memory circuit designers and professional software engineers in a fast paced project oriented environment. Development will include writing behavioral, physical, and electrical models of memory circuits, and making templates for models that are integrated into a memory compiler. Duties will also include writing scripts, optimizing EDA/CAD modeling processes, and driving continuous improvements through automation. Candidate must have the abilities to prioritize well, communicate clearly, deliver solutions on-time, and possess excellent problem solving skills. Will be expected to work across multiple facets of projects, have experience with ASIC development, and juggle multiple responsibilities at the same time. Responsibilities: Candidate will design, implement, and deploy timing, behavioral, DFT, and power models used in a ASIC-type design environment. Candidate will directly help design engineers throughout the company, solve flow related issues, and work with CAD vendors (Synopsys, Cadence, Mentor, Ansys, etc.) to find solutions. This includes working with other organizations to build consensus and facilitate collaboration with teams across the US and India. Candidate will work to improve legacy memory compiler software systems which use developed-in-house applications as well as 3rd party EDA/CAD tools. Candidate will also work to insure the quality of generated models by developing test methods. Candidate will respond to support calls, tickets, and emails from chip designers throughout Broadcom. Qualifications: The minimum engineering experience required is typically a BS degree in EE/CS/CE with programming/coding experience with 8 years of industry experience, or an MS degree with 6 or Ph.D. degree in EE/CS with 3 years of industry experience. Verilog modeling skills Static & Dynamic timing analysis knowledge. Experience with chip design tools and design flows, such as: DFT: Tessent, LogicVision, Modus, manufacturing test flows: at-speed scan test, Logic BIST, Memory BIST Synthesis: Design Compiler, Genus. Simulation: VCS, Questa, Verilog, waveform viewers, and simulation debug. STA: Primetime, Tempus, Celtic, Velocity. Power Analysis: Redhawk, Voltus, PowerCompiler, Power Artist. P&R: ICC, Innovus, Olympus, Encounter. Knowledge of circuit simulation (SPICE). Knowledge of CMOS fabrication methods and digital circuits. Strong Linux skills required. Strong scripting skills (Perl and/or Python, plus shell scripting) required. Strong analytical skills Strong communication skills Strong multi-tasking skills Optimistic yet pragmatic attitude Demonstrable skills for quick ramp-up Extremely detailed oriented, organized and methodical Ability to stay calm under pressure Team player Able to work with minimum supervision and handle ambiguity - provided by Dice CAD, EDA, DFT, STA, Primetime, Tempus, redhawk, BIST, etc

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