Principal Engineer-Verification (Networking)
Company Description Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products. Job Description Microchip Technology Inc. has a Principal Engineer-Verification position based in Chandler, AZ within the Microchip USB & Networking Group (UNG) team. The successful candidate will work on pre-silicon verification of High-Speed Transceiver (HST) Products and sub-systems - our next generation Ethernet PHYs (Physical layer devices).
Responsibilities:
o Perform ASIC/SOC verification at sub-system and full chip level. o Involve in test bench architecture and development in SV-UVM, comprehensive test plan development. o Involve in development of test sequences, test cases. o Perform RTL and back-annotated simulations and debug. o Define and develop effective functional SV assertions and cover points. o Implement solutions to automate the verification flow. o Review of Architectural, Micro-Architectural specifications. o Support post-silicon validation efforts. o Interface with cross-functional teams to understand the use-cases and develop test scenarios around them. Job Requirements o Bachelor's degree with 8.5
years of experience in digital verification. o Extensive knowledge of verification flows and techniques at the RTL and gate level simulation using SV/UVM flows. o Hands on experience in debugging complex test bench environments, EDA tools. o Capable of debugging design related issues. o Good understanding of SV assertions and coverage. o Good understanding of digital design fundamentals. o Proficiency with UNIX-based scriptinglanguages (Perl, Python, TCL, AWK, CSH). o Excellent written and verbal communication skills and documentation skills. o Self-motivated, able to work independently or as part of a team. Preferred
Qualifications:
o Knowledge of Ethernet protocols. o Hands on experience in creating SV-UVM based verification environments.
Salary Range:
$100K -- $150K
Minimum Qualification
System & Network AdministrationEstimated Salary: $20 to $28 per hour based on qualifications.
Responsibilities:
o Perform ASIC/SOC verification at sub-system and full chip level. o Involve in test bench architecture and development in SV-UVM, comprehensive test plan development. o Involve in development of test sequences, test cases. o Perform RTL and back-annotated simulations and debug. o Define and develop effective functional SV assertions and cover points. o Implement solutions to automate the verification flow. o Review of Architectural, Micro-Architectural specifications. o Support post-silicon validation efforts. o Interface with cross-functional teams to understand the use-cases and develop test scenarios around them. Job Requirements o Bachelor's degree with 8.5
years of experience in digital verification. o Extensive knowledge of verification flows and techniques at the RTL and gate level simulation using SV/UVM flows. o Hands on experience in debugging complex test bench environments, EDA tools. o Capable of debugging design related issues. o Good understanding of SV assertions and coverage. o Good understanding of digital design fundamentals. o Proficiency with UNIX-based scriptinglanguages (Perl, Python, TCL, AWK, CSH). o Excellent written and verbal communication skills and documentation skills. o Self-motivated, able to work independently or as part of a team. Preferred
Qualifications:
o Knowledge of Ethernet protocols. o Hands on experience in creating SV-UVM based verification environments.
Salary Range:
$100K -- $150K
Minimum Qualification
System & Network AdministrationEstimated Salary: $20 to $28 per hour based on qualifications.
|
|
 | |
